View HV9110NG-G_1188021.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HV9110 High-Voltage Current-Mode PWM Controller
Features
10V to 120V Input Voltage Range Current-mode control High efficiency Up to 1.0MHz internal oscillator Internal start-up circuit Low internal noise
General Description
The Supertex HV9110 is a BiCMOS/DMOS single-output, pulse width modulator IC intended for use in high-speed, high-efficiency switch mode power supplies. It provides all the functions necessary to implement a single-switch current mode PWM, in any topology, with a minimum of external parts. Because the HV9110 utilizes Supertex's proprietary BiCMOS/ DMOS technology, it requires less than one tenth of the operating power of conventional bipolar PWM ICs, and can operate at more than twice their switching frequency. The dynamic range for regulation is also increased, to approximately 8 times that of similar bipolar parts. It starts directly from any DC input voltage between 10 and 120VDC, requiring no external power resistor. The output stage is push-pull CMOS and thus requires no clamping diodes for protection, even when significant lead length exists between the output and the external MOSFET. The clock frequency is set with a single external resistor. Accessory functions are included to permit fast remote shutdown (latching or nonlatching) and under voltage shutdown.
Applications
DC/DC converters Distributed power systems ISDN equipment PBX systems Modems
Ordering Information
Device HV9110 Package Option 14-Lead Narrow Body SOIC (NG) HV9110NG-G
For similar ICs intended to operate directly from up to 450VDC input, please consult the data sheets for the HV9120 and HV9123. For detailed circuit and application information, please refer to application notes AN-H13 and AN-H21 to AN-H24.
-G indicates package is RoHS compliant (`Green')
Pin Configuration
OSC IN DISCHARGE VREF SHUTDOWN RESET COMP FB OSC OUT
Absolute Maximum Ratings
Parameter Input voltage, VIN Logic voltage, VDD Logic linear input, FB and sense input voltage Storage temperature Power dissipation Value 120V 15.5V -0.3V to VDD +0.3V -65C to +150C 750mW
VDD -VIN OUTPUT SENSE +VIN BIAS
14-Lead Narrow Body SOIC (NG)
Product Marking
Top Marking
HV9110NG
YWW LLLLLLLL
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Bottom Marking
CCCCCCCCC AAA
Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = "Green" Packaging
*May be part of top marking
14-Lead Narrow Body SOIC (NG)
HV9110
Electrical Characteristics
(Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390K, ROSC = 330K, TA = 25C.)
Sym Reference
Parameter
#
Min
Typ
Max
Units
Conditions
VREF ZOUT ISHORT VREF Oscillator fMAX fOSC PWM DMAX Oscillator frequency Initial accuracy(1) Voltage stability Temperature coefficient # Output voltage Output impedence Short circuit current Change in VREF with temperature # #
3.92 3.82 15 -
4.00 4.00 30 125 0.25
4.08 4.16 45 250 V K A mV/C
RL = 10M RL = 10M TA = -55C to 125C --VREF = -VIN TA = -55C to 125C ROSC = 1.0M ROSC = 330K ROSC = 150K VSYNC = 0.1V TA = -55C to 125C ---------
1.0 80 160 -
3.0 100 200 170
120 240 15 -
MHz KHz % ppm/C
Maximum duty cycle Deadtime
# #
49.0 -
49.4 80
49.6 0 125
% ns % ns
DMIN
Minimum duty cycle Maximum pulse width before pulse drops out
Current Limit Maximum input signal tD Delay to output # 1.0 1.2 80 1.4 120 V ns VFB = 0V VSENSE = 1.5V, VCOMP 2.0V VFB shorted to comp VFB = 4.0V --------VFB = 3.4V VFB = 4.5V ---
Error Amplifier VFB IIN VOS AVOL GB ZOUT ISOURCE ISINK PSRR Feedback voltage Input bias current Input offset voltage Open loop voltage gain Unity gain bandwidth Out impedance Output source current Output sink current Power supply rejection # # # # -1.4 0.12 3.96 4.00 25 4.04 500 V nA dB MHz mA mA dB
nulled during trim 60 1.0 80 1.3 see Fig. 1 -2.0 0.15 see Fig. 2
Notes: # Guaranteed by design. Not subject to production test. (1) Stray capacitance on OSC In pin must be 5pF.
2
HV9110
Electrical Characteristics (cont.)
(Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390K, ROSC = 330K, TA = 25C.)
Sym
Parameter
#
Min
Typ
Max
Units
Conditions
Pre-regulator/Startup +VIN +IIN VTH VLOCK Supply IDD IQ IBIAS VDD tSD tSW tRW tLW VIL VIH IIH IIL Output VOH Output high voltage VOL Output low voltage Pull up ROUT Output resistance Pull down Pull up Pull down tR tF Rise time Fall time # # VDD - 0.25 VDD - 0.3 15 8.0 20 10 30 20 0.2 0.3 25 20 30 30 75 75 V V V V ns ns IOUT = 10mA IOUT = 10mA, TA = -55C to 125C IOUT = -10mA IOUT = -10mA, TA = -55C to 125C IOUT = 10mA IOUT = 10mA, TA = -55C to 125C CL = 500pF CL = 500pF Supply current Quiescent supply current Nominal Bias current Operating range 9.0 0.75 0.55 20 1.0 13.5 mA mA A V CL < 75pF Shutdown = -VIN ----Input voltage Input leakage current Vdd pre-regulator turn-off threshold voltage Undervoltage lockout 10 8.0 7.0 8.7 8.1 120 10 9.4 8.9 V A V V IIN < 10A; VCC > 9.4V VDD > 9.4V IPREREG = 10A ---
Shutdown Logic Shutdown delay Shutdown pulse width RESET pulse width Latching pulse width Input low voltage Input high voltage Input current, input high voltage Input current, input low voltage # # # # 50 50 25 7.0 50 1.0 -25 100 2.0 5.0 -35 ns ns ns ns V V A A --Shutdown and reset low ----VIN = VDD VIN = 0V CL = 500pF, VSENSE = -VIN
Notes: # Guaranteed by design. Not subject to production test.
3
HV9110
Truth Table
Shutdown H H L L LH Reset H HL H L L Output Normal operation Normal operation, no change Off, not latched Off, latched Off, latched, no change
Shutdown Timing Waveforms
1.5V Sense 0 td VDD Output 0 t SW 50% 0 t LW VDD Reset 50% 0 t RW 50% 50% 50% tR, tF 10ns 90% Output VDD 0 50% tR 10ns Shutdown 0 t SD 90% VDD 50% tF 10ns
VDD Shutdown
Functional Block Diagram
FB 14 (19) COMP 13 (18) Error Amplifier - 10 (14) VREF + 4V REF GEN + S + - 1 (20) BIAS 6 (9) VDD 2 (3) +VIN - + 8.1V 8.6V - + Undervoltage Comparator Q R 12 (17) Reset 11 (16) S Shutdown Current Sources To Internal Circuits Current Limit Comparator 5 (8) -VIN 2V - Modulator Comparator T R Q Q To VDD 4 (6) Output OSC Discharge 9 (12) OSC IN 8 (11) OSC OUT 7 (10)
1.2V 3 (5) VDD Current Sense
Pre-regulator/Startup
4
HV9110
Typical Performance Curves
Fig. 1
10
6
Error Amplifier Output Impedance (Z0)
Fig. 4
1M
Output Switching Frequency vs. Oscillator Resistance
105 104 103 102
fOUT (Hz)
ZO ()
100k
10
1
.1
100Hz 1KHz 10KHz 100KHz 1MHz 10MHz
10k 10k
100 k
1M
Frequency
ROSC ()
Fig. 2
0 -10 -20 -30
PSRR -- Error Amplifier and Reference
Fig. 5
80 70 60 50
Error Amplifier Open Loop Gain/Phase
180 120 60 0 -60 -120 -180
PSSR (dB)
40 30 20 10 0 -10
-40 -50 -60 -70 -80 10 100 1K 10K 100K 1M
100
1K
10K
100K
1M
Frequency (Hz)
Frequency (Hz) RDISCHARGE vs. tOFF (9113 only)
Fig. 3
100
Fig. 6
104
Bias Current (A)
VDD = 12V 10
ROSC = 100K
tOFF (nsec)
VDD = 10V
103
ROSC = 10K
ROSC = 1K 1 105 10
6
107
102 10-1
100
101
102
103
104
105
106
Bias Resistance ()
RDISCHARGE ()
5
Phase (C)
Gain (dB)
HV9110
Test Circuits
Error Amp ZOUT
+10V (VDD) 1.0V swept 100Hz - 2.2MHz 60.4K
-
0.1V swept 10Hz - 1MHz
PSRR
100K1% 10.0V 100K1% 4.00V
- +
(FB) Reference GND (-VIN) 0.1F
+
V1
Tektronix P6021 (1 turn secondary)
V1
V2 40.2K
Reference 0.1F
V2
NOTE: Set Feedback Voltage so that VCOMP = VDIVIDE 1mV before connecting transformer
Detailed Description
Preregulator
The preregulator/startup circuit for the HV9110 consists of a high-voltage n-channel depletion-mode DMOS transistor driven by an error amplifier to form a variable current path between the VIN terminal and the VDD terminal. The maximum current (about 20 mA) occurs when VDD = 0, with current reducing as VDD rises. This path shuts off altogether when VDD rises to somewhere between 7.8 and 9.4V, so that if VDD is held at 10 or 12V by an external source(generally the supply the chip is controlling). No current other than leakage is drawn through the high voltage transistor. This minimizes dissipation. An external capacitor between VDD and VSS is generally required to store energy used by the chip in the time between shutoff of the high voltage path and the VDD supply's output rising enough to take over powering the chip. This capacitor should have a value of 100X or more the effective gate capacitance of the MOSFET being driven, i.e., CSTORAGE 100 x (gate charge of FET at 10V / 10V) as well as very good high frequency characteristics. Stacked polyester or ceramic caps work well. Electrolytic capacitors are generally not suitable. A common resistor divider string is used to monitor VDD for both the under voltage lockout circuit and the shutoff circuit of the high voltage FET. Setting the under voltage sense point about 0.6V lower on the string than the FET shutoff point guarantees that the under voltage lockout always releases before the FET shuts off.
Bias Circuit
An external bias resistor, connected between the BIAS pin and VSS is required by the HV9110 to set currents in a series of current mirrors used by the analog sections of the chip. The nominal external bias current requirement is 15 to 20A, which can be set by a 390K to 510K resistor if a 10V VDD is used, or a 510k to 680K resistor if VDD will be 12V. A precision resistor is not required; 5% is fine.
Clock Oscillator
The clock oscillator of the HV9110 consists of a ring of CMOS inverters, timing capacitors, a capacitor discharge FET, and, in the 50% maximum duty cycle versions, a frequency dividing flip-flop. A single external resistor between the OSC IN and OSC OUT is required to set the oscillator frequency (see graph). For the 50% maximum duty cycle versions the Discharge pin is internally connected to GND. For the 99% duty cycle version, the Discharge pin can either be connected to VSS directly or connected to VSS through a resistor used to set a deadtime. One major difference exists between the Supertex HV9110 and competitive 9110's. On the Supertex part, the oscillator is shut off when a shutoff command is received. This saves about 150A of quiescent current, which aids in the construction of power supplies that meet CCITT specification I-430, and in other situations where an absolute minimum of quiescent power dissipation is required.
6
HV9110
Reference
The Reference of the HV9110 consists of a stable bandgap reference followed by a buffer amplifier which scales the voltage up to approximately 4.0V. The scaling resistors of the reference buffer amplifier are trimmed during manufacture so that the output of the error amplifier, when connected in a gain of -1 configuration, is as close to 4.0V as possible. This nulls out any input offset of the error amplifier. As a consequence, even though the observed reference voltage of a specific part may not be exactly 4.0V, the feedback voltage required for proper regulation will be. A 50K resistor is placed internally between the output of the reference buffer amplifier and the circuitry it feeds (reference output pin and non-inverting input to the error amplifier). This allows overriding the internal reference with a low impedance voltage source 6.0V. Using an external reference reinstates the input offset voltage of the error amplifier, and its effect of the exact value of feedback voltage required. Because the reference of the HV9110 is a high impedance node, and usually there will be significant electrical noise near it, a bypass capacitor between the reference pin and VSS is strongly recommended. The reference buffer amplifier is intentionally compensated to be stable with a capacitive load of 0.01 to 0.1F.
Current Sense Comparators
The HV9110 uses a true dual comparator system with independent comparators for modulation and current limiting. This allows the designer greater latitude in compensation design, as there are no clamps (except ESD protection) on the compensation pin. Like the error amplifier, the comparators are of low-noise BiCMOS construction.
Remote Shutdown
The shutdown and reset pins of the 9110 can be used to perform either latching or non-latching shutdown of a converter as required. These pins have internal current source pull-ups so they can be driven from open drain logic. When not used they should be left open, or connected to VDD.
Output Buffer
The output buffer of the HV9110 is of standard CMOS construction (P-channel pull-up, N-channel pull-down). Thus the body-drain diodes of the output stage can be used for spike clipping if necessary, and external Schottky diode clamping of the output is not required.
Error Amplifier
The error amplifier in the HV9110 is a true low-power differential input operational amplifier intended for around the amplifier compensation. It is of mixed CMOS-bipolar construction: A PMOS input stage is used so the common mode range includes ground and the input impedance is very high. This is followed by bipolar gain stages which provide high gain without the electrical noise of all-MOS amplifiers. The amplifier is unity gain stable.
7
HV9110
14-Lead SOIC (Narrow Body) Package Outline (NG)
8.65x3.90mm body, 1.27mm pitch
14
D
1
Note 1 (Index Area D/2 x E1/2)
E1
E
L2 Gauge Plane
1 L1
L
Seating Plane
Top View
A
View B
h View B
A A2 e
Seating Plane b A
h
Note 1
A1
Side View
View A-A
Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
A 1.35 1.75
A1 0.10 0.25
A2 1.25 1.65
b 0.31 0.51
D 8.55 8.65 8.75
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e 1.27 BSC
h 0.25 0.50
L 0.40 1.27
L1 1.04 REF
L2 0.25 BSC
0
O
1 5O 15O
8
O
JEDEC Registration MS-012, Variation AB, Issue E, Sept. 2005. Drawinngs not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV9110 A101007
8

▲Up To Search▲

Price & Availability of HV9110NG-G

	To Download HV9110NG-G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .